1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor device mounting apparatus and methods.
2. Description of the Related Art
Conventional integrated circuits are frequently implemented on a semiconductor substrate or die that consists of a small rectangular piece of semiconductor material, typically silicon, fashioned with two opposing principal sides. The active circuitry for the die is concentrated near one of the two principal sides. The side housing the active circuitry is usually termed the “active circuitry side,” while the side opposite the active circuitry side is often termed the “bulk silicon side.” Depending on the thermal output of the die, it may be desirable to mount a heat transfer device, such as a heat sink, on the bulk silicon side of the die. This mounting may be directly on the bulk silicon side or on a lid that is positioned over the die.
A conventional die is usually mounted on some form of substrate, such as a package substrate or a printed circuit board. Electrical connectivity between the die and the underlying substrate or board is established through a variety of conventional mechanisms. In a so-called flip-chip configuration, the active circuitry side of the die is provided with a plurality of conductor balls or bumps that are designed to establish a metallurgical bond with a corresponding plurality of conductor pads positioned on the substrate or circuit board. The die is flipped over and seated with the active circuitry side facing downwards on the underlying substrate. A subsequent thermal process is performed to establish the requisite metallurgical bond between the bumps and the pads. One of the principal advantages of a flip-chip mounting strategy is the relatively short electrical pathways between the integrated circuit and the substrate. These relatively low inductance pathways yield a high speed performance for the electronic device.
In some circumstances it may make sense from a performance standpoint to stack one semiconductor die on another semiconductor die. For example, it may be advantageous to mount a memory device on a processor device. However, electrical interconnects must be established between the stacked dice. Several conventional techniques for stacking dice have been considered.
In one conventional variant, a relatively small semiconductor die is positioned on the bulk semiconductor side of a much larger semiconductor die. Bonding wires are used to establish the electrical conductivity between the upper die and the lower die. The difficulty associated with this approach is that the bonding wires tend to be relatively long electrical pathways and thus exhibit higher than desired inductance and proportionally slower electrical performance. In addition, the bulk semiconductor side is not available for heat sink mounting.
In another conventional variant, a relatively small die is flip-chip mounted on the bulk silicon side of a larger semiconductor die. Electrical interconnects between the upper and lower die are provided by a plurality of conductor traces that are formed on the bulk silicon side of the lower die. As with the first-mentioned conventional design, the conductor traces represent relatively high inductance pathways and thus limit speed performance. Furthermore, the bulk silicon side is not available for a heat sink.
In still another conventional design, a second die is mounted on the bulk silicon side of a larger die. Electrical interconnects between the two are established through a plurality of silicon vias. This design also requires a plurality of external traces and thus represents longer than desired electrical pathways for signal transfer. In addition, the bulk silicon side is not available for a heat sink.
A fourth conventional design consists of a first die upon which a couple of additional dice are positioned. The multiple smaller dice are electrically interconnected with each other and with the larger base die by way of a metal layer that is patterned on the base die and the two top-mounted dice. The metal layer is not unlike a larger scale version of a typical metallization layer used in a semiconductor die. In this regard, a dielectric layer is typically formed over the base die and the multiple top-mounted dice. The dielectric layer is lithographically patterned with openings to selected portions of the base and top-mounted dice. The metallization layer is thereafter deposited over the dielectric layer. This conventional technique requires a very high degree of die alignment, which is not always possible and thus may result in limited yields.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.